(a) Field of the Invention
The present invention relates to a DRAM (dynamic random access memory) having a stacked capacitor in each memory cell and a method for fabricating such a DRAM.
(b) Description of the Related Art
At the developing stage of DRAMs where the degree of integration is relatively low, the stacked capacitor disposed in each memory cell of the DRAM is generally formed by a top electrode made of polycrystalline silicon (polysilicon), a bottom electrode made of polysilicon and a capacitor dielectric film interposed therebetween and made of silicon oxide or a three-layer structure (ONO film) including silicon oxide layer/silicon nitride layer/silicon oxide layer.
With the development of higher integration and finer patterning in the DRAMs, the stacked capacitor as well as the MOSFETs should be subjected to a finer patterning process. In a 256 mega-bit (Mb) DRAM, or of higher integration, for example, the capacitor dielectric film should have a thickness lower than 4 nm when a silicon oxide film or ONO film having a relatively low permittivity (dielectric constant) is used in the stacked capacitor. However, it is quite difficult or substantially impossible to achieve such a smaller thickness in the silicon oxide film or ONO film from the technical view point, such as suppression of leakage current through the thin capacitor dielectric film. Thus, it is desired to make the stacked capacitor to be smaller and have a higher capacity by using a (Ba, Sr)TiO3 film (BST film) having a higher dielectric constant as the capacitor dielectric film and by using a oxidation-resistant conductor as the bottom electrode.
FIG. 1 shows the memory cell array of a DRAM, wherein a plurality of word lines 82 extend in a row direction, and a plurality of bit lines 38 extend in a column direction. Each word line 82 is connected to the gates of MOSFETs of a corresponding row of memory cells, whereas each bit line 38 is connected to the diffused regions of MOSFETs of a corresponding column of memory cells. A plurality of capacitor contacts 18 are disposed between adjacent word lines 82 for connecting bottom electrodes with the diffused regions of corresponding MOSFETs, whereas a plurality of bit contacts 57 are aligned with the bit lines 38 between adjacent bottom electrodes 28 for connecting the diffused regions of the MOSFETs 14 and the bit lines 38. The area encircled by a dotted line corresponds to a unit memory cell, which occupies an area of 8xc3x97(F+M)2, wherein F is the minimum design width of the word lines 82 and the bit lines 38 and M is a design margin for patterning. In the current photolithographic technique, M is generally above 0.05 xcexcm for F=0.18 xcexcm
FIGS. 2 and 3 are cross-sectional views taken along lines Axe2x80x94A and Bxe2x80x94B, respectively, in FIG. 1. The conventional DRAM 10 includes a p-type silicon substrate 12, a plurality of MOSFETs 14 each disposed in an isolated region of the silicon substrate 12 isolated from another isolated region by a field oxide film 13, a dielectric film 16 made of SiO2 etc. covering the MOSFETs 14, a stacked capacitor 20 disposed above the MOSFET 14 and having a top electrode 32, a bottom electrode 28 and a capacitor dielectric film 30, a capacitor contact 18 disposed in a via hole for connecting the bottom electrode 28 and the diffused region 36 of the MOSFET 14 in each memory cell.
The capacitor contact 18 includes polysilicon plug 22 disposed on the diffused region 36 in a via hole, and a silicide contact layer 24 and a silicon-diffusion-resistant conductive layer 26 consecutively disposed on top of the polysilicon plug 22. The silicon-diffusion-resistant conductive layer 26 includes a high-melting-point metal (refractory metal) or its nitride TiN or WN of such a metal, and is disposed for prevention of formation of a silicide metal between the metallic bottom electrode 28 and the capacitor contact 18. The silicide contact layer 24 is made of TiSi2, for example, which improves adhesion and reduces the contact resistance between the silicon-diffusion-resistant conductive layer 26 and the polysilicon plug 22.
The bottom electrode 28 of the capacitor 20 is made of a solid conductor made of oxidation-resistant conductive material, such as a noble metal (Pt etc.), Ru or a metal oxide such as RuO2, the capacitor dielectric film 30 is made of BST having a high dielectric constant, and the top electrode 32 is made of the metal same as the metal of the bottom electrode 28.
The MOSFET 14 has a gate electrode 34 formed on the gate oxide film 33, and a pair of n-type diffused regions 36 implementing source/drain regions and sandwiching the gate electrode 34 therebetween as viewed in the vertical direction. Bit lines 38 are shown in FIG. 3 within the SiO2 film 16 having via holes receiving therein the capacitor contacts 18. The bottom electrode 28 of the stacked capacitor 20 is connected to the diffused region 36 of the MOSFET 14 through the capacitor contact 18.
Referring to FIGS. 4A to 4H, there are shown cross-sections of the DRAM of FIG. 1 for illustrating consecutive steps of fabrication of the stacked capacitor. As shown in FIG. 4A, after MOSFETs are formed on a silicon substrate 12, a dielectric film 16 made of SiO2 is deposited by a CVD technique, followed by formation of via holes 40 therein. A polysilicon film 39 is then deposited by a CVD technique, followed by ion-implantation of phosphorous ions thereto to reduce the resistivity of the polysilicon film 39.
Thereafter, as shown in FIG. 4B, the polysilicon film 39 is subjected to an etch-back step to expose the top of the dielectric film 16, and also subjected to over-etch to remove the top portion of the polysilicon film 39 in the via holes 40, thereby leaving the polysilicon plug 22 in the via holes 40.
Subsequently, as shown in FIG. 4C, a Ti film 42 is deposited on the entire surface including the top of the polysilicon plug 22 by sputtering, followed by rapid thermal annealing (RTA) in a nitrogen ambient, thereby forming a silicide contact layer 24 made of TiSi on the top of the polysilicon plug 22. After removing the unreacted Ti on the dielectric film 16 and in the via holes 40 to expose the dielectric film 16 and the TiSi film 24, a TiN film 44 is deposited on the TiSi film 24 and the dielectric film 16 by a CVD technique or a sputtering technique.
The TiN film 44 is then subjected to a chemical-mechanical polishing (CMP) process using colloidal silica, thereby exposing the dielectric film 16 and achieving the capacitor contact 18 including the silicon-diffusion-resistant conductive layer 26, TiSi contact layer 24 and polysilicon plug 22 in the via hole 40.
Thereafter, a Ru film is deposited on the dielectric film 16 and the capacitor contacts 18 by using a reactive DC sputtering process, followed by selective etching thereof to form a bottom electrode 28 on top of the capacitor contact 18 by a plasma etching technique using an etching mask and a mixed gas of chlorine and oxygen. The bottom electrode 28 is solid and of a block-like shape, as shown in FIG. 4F.
Next, a MOCVD process using Ba(DPM)2, Sr(DPM)2, Ti(i-OC3H7) and oxygen is conducted to form an about 30-nm-thick BST film as a capacitor dielectric film 30 on the entire surface of the substrate. xe2x80x9cDMPxe2x80x9d as used herein means bis-dipivaloylmethanate. In this step, the substrate temperature is maintained between 400 and 700 xc2x0 C., with the gas pressure maintained at about 7 mTorr.
Then, another Ru film is deposited on the BST film by using a reactive DC sputtering to thereby form a top electrode 32. Thus, a DRAM 10 of FIG. 1 including a stacked capacitor having a BST film as the capacitor dielectric film 30 is obtained.
In the conventional DRAM as described above, the bottom electrode 28 should be patterned so that the bottom electrode 28 covers the top of the capacitor contact 18 in order that the BST film implemented as the capacitor dielectric film 30 do not contact with the capacitor contact 18. The reason therefor will be further described with reference to FIGS. 5 and 6.
In FIGS. 5 and 6 showing the top plan view and cross-sectional view, respectively, of the DRAM 10, if the bottom electrode 28 misaligns to the top of the capacitor contact 18 to expose the silicon-diffusion-resistant conductive layer 26, the silicon-diffusion-resistant conductive layer 26 is subjected to oxidation due to the oxidizing ambient during deposition of the BST film 30, whereby the electric resistance of the silicon-diffusion-resistant conductive layer 26 increases.
For prevention of the surface of the silicon-diffusion-resistant conductive layer 26 from being exposed, the bottom electrode 28 must be aligned with the location of the capacitor contact 18. This necessitates a larger design margin for the etching mask used for patterning the bottom electrode 28. In FIG. 5, the area of the unit cell or memory cell is expressed by 2Fpxc3x974Fp wherein Fp is a half of the pitch of the bit lines and Fp=(F+M), F and M being the minimum design width of the lines (or minimum design rule) and the design margin for alignment, respectively. Thus, the area of the unit memory cell, which is expressed by 2Fpxc3x974Fp=8xc3x97(F+M)2 as shown in FIG. 5 increases with the increase of the design margin.
FIG. 7 shows design sizes of the DRAMs plotted against the generations of the DRAMs. With higher integration of the DRAMs, the minimum design rule F and the design margin M decrease, with the required accuracy for alignment being also reduced in terms of size (xcexcm). In this situation, the current fabrication technique does not match the higher integration of the DRAMs. The accuracy of the alignment is especially required in the direction normal to the longitudinal direction of the bottom electrode 28.
The above situation is similar to DRAMs having a capacitor dielectric film made of other than the BST film, although the conventional DRAM having a BST film is exemplarily described herein.
It is therefore an object of the present invention to provide a DRAM having a stacked capacitor, which is capable of being fabricated with a simplified process and with a finer design rule.
It is another object of the present invention to provide a method for fabricating the DRAM as described above.
The present invention provides a DRAM including a plurality of memory cells each including a MOSFET having a gate electrode and a pair of diffused regions, a stacked capacitor having a bottom electrode of a cylindrical shape, a top electrode, at least a portion of the top electrode being received in the bottom electrode, and a capacitor dielectric film sandwiched between the top electrode and the bottom electrode, and a capacitor contact for connecting one of the diffused regions to the bottom electrode,
The present invention also provides a method for manufacturing a DRAM including the steps of:
forming a MOSFET having a gate and a pair of diffused regions in an isolated region of a silicon substrate;
forming a first dielectric film covering the MOSFET and having a via hole receiving therein a capacitor contact in contact with one of the diffused regions;
forming, on the first dielectric film, a second dielectric film including an opening having a bottom exposing a top of the capacitor contact; forming a capacitor having a bottom electrode in contact with the capacitor contact in the opening of the second dielectric film.
In accordance with the DRAM of the present invention, the cylindrical shape of the bottom electrode allows a larger deviation of alignment between the capacitor and the capacitor contact with a smaller design margin, thereby facilitating simplified process for fabrication of the DRAM and improving the yield of the DRAMs. The cylindrical shape as used herein is not limited to the shape which has a circular cross-section and may have a any cross-section such as a rectangular cross-section.